The performance of MOS transistors (i.e., NMOS transistors) can oftentimes suffer as a result of the Miller effect. Due at least in part to the geometry of the MOS transistors, a gate-drain capacitance or Cdg can exist, which can affect the reverse isolation of the MOS transistor and which can hamper gain and bandwidth. This is especially true at higher frequencies where, by default, gain is lower. A conventional technique that has been employed to compensate for the Miller effect is neutralization.
Neutralization generally employs the use of a negative or neutralization capacitance. Turning to FIG. 1, an example of a transconductance circuit 100, which employs neutralization capacitances, can be seen. As shown, transconductance circuit 100 generally comprises a pair of differential input transistor Q1 and Q2 (which, as shown, are NMOS transistors and which receive the input signals INP and INM) and capacitor-connected MOS transistors or MOS capacitors Q3 and Q4 (which, as shown, are NMOS transistors). MOS capacitors Q3 and Q4 are cross-coupled between the transistors Q1 and Q2 to provide capacitances to counter the gate-drain capacitances of transistors Q1 and Q2. A metal-metal capacitor (also referred to as a flux capacitor or MIM capacitor) can be used in the place of the MOS capacitors Q3 and Q4, but, because the gate-drain capacitances of transistors Q1 and Q2 change with bias, the MOS capacitors Q3 and Q4 more accurately track the gate-drain capacitances of transistors Q1 and Q2. Additionally, MOS capacitors Q3 and Q4 are usually a fraction (i.e. ½, ⅔, etc.) of the size of the transistors Q1 and Q2.
There are, however, problems associated with this arrangement. At higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization, so the layout should be formulated such that the parasitic inductance at the frequency of interest is low (i.e., close to zero). Such a layout, though, can be difficult to design for millimeter wave or terahertz applications. Thus, there is a need for a layout for a transconductance circuit that compensates for the Miller effect at high frequencies.
Some other conventional circuits are: U.S. Pat. No. 7,355,479; and U.S. Patent Pre-Grant Publ. No. 2007/0046376.